Semiconductor memory comprises a plurality of rows of memory cells arranged in columns, the number of which depends on the storage capacity of the storage unit. With the increase of the storage unit, the probability of failure of the memory cell also increases. When a storage unit fails, the semiconductor memory device cannot be used.
Test techniques for memory systems conventionally include the application of predetermined input bit patterns to memory cells of the memory system, and thereafter reading the contents of the memory cells to determine whether the output patterns match the input patterns. If the output patterns do not match the input patterns, it follows that a fault has occurred somewhere in the memory system.
Memory systems, however, are becoming increasingly complex, and the above conventional input/output pattern matching technique does not offer an adequate level of fault isolation for such complex memory systems. What is required, therefore, are test/verification methods and systems which provide a greater degree of fault isolation for complex memory systems.